library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity traffic is port ( clk: instd_logic; dataout: outstd_logic_vector(11downto0)); end traffic; architecture q1 of traffic is type state_type is(s1,s2,s3,s4); signal state:state_type; signal ti:integerrange0to5:=0; begin process(clk) begin if (clk'eventand clk='1') then case state is when s1=>if ti=5then ti<=0; state<=s2; else state<=s1; ti<=ti+1; endif; when s2=>if ti=3then ti<=0; state<=s3; else state<=s2; ti<=ti+1; endif; when s3=>if ti=5then ti<=0; state<=s4; else state<=s3; ti<=ti+1; endif; when s4=>if ti=3then ti<=0; state<=s4; else state<=s1; ti<=ti+1; endif; whenothers=>state<=s1; endcase; endif; endprocess; process(state) begin case state is when s1=>dataout<="100001100001"; when s2=>dataout<="100010100010"; when s3=>dataout<="001100001100"; when s4=>dataout<="010100010100"; endcase; endprocess; end q1;