四人抢答器

一、实验目的

掌握模块设计方法；
掌握采用刷新方式控制多个数码管显示的方法。

二、实验电路图

三、实验内容

设计一个4人参加的抢答器，当有一个选手首先按下抢答器开关时，相应在一个数码管上显示该选手所在的开关编号，此时抢答器不再接受其他人的输入信号，同时启动计时功能，采用到计时的方式在2个数码管上显示时间，时间最长为100S，显示为99～00，当到达00时，用一个发光二极管提醒，并不再计时。另外系统设计一个开关，用来复位。
本实验要求同时显示3个数码管，但实际一个时刻只能显示一个数码管，所以只能采用刷新的方式，刷新频率要足够快（600Hz以上）；时钟可用一个秒计数器实现；另外加一个数码数字转换模块和按键输入检测电路（即抢答控制），这部分可以参考上个实验。
根据实验要求，可以采用多模块的方式设计，下图是建议划分的模块，也可以自行设计模块。

四、实验连线

实验连线同彩灯控制实验

五、实验结果

拨动开关，数码管上观看抢答情况。

我的vhdl代码

①主程序：FourManQuest

library ieee;
use ieee.std_logic_1164.all;
entity FourManQuest is
	port (K: in std_logic_vector (3 downto 0);
			clk_5: in STD_LOGIC;
			clk_2: in STD_LOGIC;
			reset: in STD_LOGIC;
			L_ABC: buffer STD_LOGIC_VECTOR(2 DOWNTO 0);
			LED: out STD_LOGIC_VECTOR (7 downto 0));
end;
architecture behave of FourManQuest is
component CTL
PORT(K: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
			reset:		IN STD_LOGIC;
			en : OUT STD_LOGIC;
		    D  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;
component SLT_4
	PORT(KD, QL, QH: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	X, Y: IN STD_LOGIC;
	D: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end component; 
component CNT_100
     PORT (reset,clk,en: IN STD_LOGIC;
                 light: OUT STD_LOGIC;
                 qh,ql: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;	 
component  CNT_4
 	PORT(CLK: IN STD_LOGIC;
        L_ABC: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
end component; 
component LED_8
	port (A: in std_logic_vector (3 downto 0);
	LED: out std_logic_vector (7 downto 0));
end component;
Signal en: STD_LOGIC;
Signal light: STD_LOGIC;
Signal D  : STD_LOGIC_VECTOR(3 DOWNTO 0);
Signal DL : STD_LOGIC_VECTOR(3 DOWNTO 0);
Signal qh : STD_LOGIC_VECTOR(3 DOWNTO 0);
Signal ql : STD_LOGIC_VECTOR(3 DOWNTO 0);
-- Signal L_ABC:STD_LOGIC_VECTOR(2 DOWNTO 0);
	begin
		ctl_c: CTL port map(K, reset, en, D);
		cnt_100_c: CNT_100 port map(reset, clk_5, en, light, qh, ql);
		cnt_4_c: CNT_4 port map(clk_2, L_ABC);
		slt_4_c: SLT_4 port map(D, ql, qh, L_ABC(1), L_ABC(0), DL);
		led_8_c: LED_8 port map(DL, LED);
end behave;

②SLT_4：

LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee. STD_LOGIC_unsigned.ALL;
ENTITY SLT_4 IS
	PORT(KD, QL, QH: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	X,Y:IN STD_LOGIC;
	D: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;
ARCHITECTURE maxpld OF SLT_4 IS
Signal S: integer;
begin
   WITH S SELECT
   D <= KD WHEN  0,
            QL WHEN 1,
            QH WHEN 2,
            "0000" WHEN OTHERS;
	S <= 0 WHEN  X = '0' AND Y = '0' ELSE
      1 WHEN X = '0' AND Y = '1' ELSE
      2 WHEN X = '1' AND Y = '0' ELSE
      3 ;
END maxpld;

③LED_8：

library ieee;
use ieee.std_logic_1164.all;
entity LED_8 is
	port(A: in std_logic_vector(3 downto 0);
	LED: out std_logic_vector(7 downto 0));
end;
architecture one of LED_8 is
begin
	process(A)
	begin
	case A is
		when "0000"=> LED <="00111111";
		when "0001"=> LED <="00000110";
		when "0010"=> LED <="01011011";
		when "0011"=> LED <="01001111";
		when "0100"=> LED <="01100110";
		when "0101"=> LED <="01101101";
		when "0110"=> LED <="01111101";
		when "0111"=> LED <="00000111";
		when "1000"=> LED <="01111111";
		when "1001"=> LED <="01101111";
		when "1010"=> LED <="01110111";
		when "1011"=> LED <="01111100";
		when "1100"=> LED <="00111001";
		when "1101"=> LED <="01011110";
		when "1110"=> LED <="01111001";
		when "1111"=> LED <="01110001";
		when others=> NULL;
		end case;
	end process;
end;

④CTL：

LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee. STD_LOGIC_unsigned.ALL;
ENTITY CTL IS
	PORT(K: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
			reset:		IN STD_LOGIC;
			en : BUFFER STD_LOGIC;
		   D:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;
ARCHITECTURE one OF CTL IS
BEGIN	
   PROCESS (reset, en, K)  
   BEGIN
   IF reset='1'  THEN  en <= '0'; D <= "0000";
	ELSIF en = '0' THEN
		case K is
		when "0001" => D <="0001";
		when "0010" => D <="0010";
		when "0100" => D <="0011";
		when "1000" => D <="0100"; 
		when others => D <="0000";
		end case;
		case K is
		when "0001" => en <= '1';
		when "0010" => en <= '1';
		when "0100" => en <= '1';
		when "1000" => en <= '1';
		when others => en <= '0';
		end case;
	END IF;
	end process;
END one;

⑤CNT_100：

LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee. STD_LOGIC_unsigned.ALL;
ENTITY CNT_100 IS
	PORT (reset,clk, en: IN STD_LOGIC;
                 light: BUFFER STD_LOGIC;
                 qh,ql: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
END;
ARCHITECTURE behave OF CNT_100 IS
BEGIN
	light <= '1' WHEN(qh = "0000" AND ql = "0000") ELSE '0';
	PROCESS (reset, clk, en, light)
		BEGIN
		IF reset = '1' THEN qh <= "1001"; ql <= "1001";
		ELSIF (  clk' EVENT AND clk = '1') THEN
			IF (en = '1' and  light = '0') THEN
				IF (ql = 0) THEN ql <= "1001";
					IF (qh = 0) THEN qh <= "1001";
					ELSE qh <= qh-1;
					END IF;
				ELSE ql <= ql-1;
				END IF;
			END IF;
		END IF;
END PROCESS;
End  behave;

⑥CNT_4：

LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee. STD_LOGIC_unsigned.ALL;
ENTITY  CNT_4  IS
 	PORT(CLK: IN STD_LOGIC;
        L_ABC: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END;
ARCHITECTURE one OF CNT_4 IS
BEGIN
PROCESS (CLK)
    VARIABLE CQI: STD_LOGIC_VECTOR (2 DOWNTO 0);
  BEGIN
   IF CLK'EVENT AND CLK='1' THEN
       CQI := CQI+1;         
   END IF;
	--IF CLK'EVENT AND CLK='1' AND CQI = 3 THEN
	IF  CQI = 3 THEN
		 CQI := "000";             
   END IF;
   L_ABC <= CQI;
   END PROCESS;
END;

引脚连接如下：

vhdl

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